The present invention relates to a COP package and a tape substrate used therein.
A driver mounted in a liquid crystal display is generally mounted in its corresponding display in a state in which a semiconductor element is being sealed onto a substrate made up of a tape. In a recent driver for a display or display unit, the proportion of a D/A converter for converting a digital signal to an analog signal within a semiconductor element is so increasing with multigradation. With the scale-up of the display unit and a reduction in the number of drivers mounted to the display unit, the number of output terminals per driver is exceeding 720. Respective companies or manufacturers involve a problem that since the recent driver needs to form so many wiring areas inside the semiconductor element in order to meet these demands, the area of the semiconductor element increases significantly.
Since a chip area is headed for its reduction contrary to the increase in the number of the output terminals, the interval between adjacent electrodes provided on a chip is becoming very narrow. With its view, there has been an increasingly demand for a COF (Chip On Film) which can be miniaturized than a TCP (Tape Carrier Package).
Disclosed in a patent document 1 (Japanese Unexamined Patent Publication No. 2006-80167) is a technique wherein with a view toward realizing a size and weight reduction in semiconductor device by paying attention to an increase in wiring in a semiconductor element, particularly, a problem that wirings must be routed or run from an electric circuit of the semiconductor element to bumps when signals are taken out from the electric circuit to the outside, semiconductor element surface bumps provided at the center of the semiconductor element corresponding to the output of the electric circuit, and bumps provided at the outer peripheral portion of the semiconductor element are respectively connected by wiring patterns provided on a substrate.
According to the present technique, since the connections between the semiconductor element circuit and the wiring patterns can be conducted even by connecting wirings, the connecting wirings can be substituted for the wirings routed at the surface or inside, thus resulting in the realization of a size and weight reduction in the semiconductor element.
In the technique disclosed in the patent document 1, however, no consideration was given to the signals inputted to the semiconductor element although the wirings relative to the output of the semiconductor element circuit can be reduced. Under the stereotype that first connecting terminals are formed at a peripheral portion on the semiconductor element in particular, the size reduction in the semiconductor element was insufficient. It also falls short of examining a structure that makes it possible to ensure reliability with a size reduction in chip.